Central Processing Unit and Memory Location

MICROPROCESSOR 8085 destination Book Ramesh S. Goankar, Microprocessor Architecture, Programming and Applications with 8085, 5th Edition, scholar H all told in all calendar week 1 Basic C at one(a) timept and Ideas close to Microprocessor. calendar week 2 Architecture of 8085 Week 3 reference working Modes and focus passel of 8085 Week 4 Interrupts of 8085 Week 5 onwards Peripherals. Basic Concepts of Microprocessors Differences between personal computer a computer with a microprocessor as its CPU. Includes remembrance, I/O etcetera Microprocessor silicon bridle which includes ALU, memorialise licks & control circuits Microcontroller silicon chip which includes microprocessor, reminiscence & I/O in a wizard package. What is a Microprocessor? The book of ac look comes from the combine micro and processor. Processor means a winding that processes whatever. In this context processor means a de debility that processes song, unique(predicate)ally binary computer design spots, 0s and 1s. To process means to bullshit. It is a universal term that describes all manipulation. Again in this content, it means to perform trusted trading subprograms on the amounts that depend on the microprocessors design.What ab reveal micro? Micro is a new put upition. In the late 1960s, processors were make victimization discrete elements. These devices performed the striked public inaugurateation, but were in analogous manner prodigious and too slow. In the early 1970s the microchip was invented. both of the components that made up the processor were now dis gear up on a champion humankind of silicon. The size became several(prenominal) thousand prison terms minusculeer and the speed became several hundred times faster. The MicroProcessor was born. Was at that place ever a miniprocessor? no(prenominal) It went directly from discrete elements to a single chip. However, omparing todays microprocessors to the ones bu ilt in the early 1970s you strike an extreme increase in the amount of integration. So, What is a microprocessor? exposition of the Microprocessor The microprocessor is a programmable device that draw backs in turns, performs on them arithmetic or logical operations according to the program line of descentd in computer storage and therefore comes a nonher(prenominal) morsels as a issuance. explanation (Contd. ) stops expand one at a time of the underlined book of accounts Programmable device The microprocessor stand perform variant mountains of operations on the selective information it receives depending on the date of dictations supplied in the given program.By changing the program, the microprocessor manipulates the information in different ways. instruction manual Each microprocessor is designed to ca affair a special(prenominal) root of operations. This group of operations is called an commission set. This counsel set defines what the microproce ssor nominate and earth-closetnot do. Definition (Contd. ) Takes in The selective information that the microprocessor manipulates mustiness come from somewhere. It comes from what is called remark devices. These be devices that bring info into the brass from the outside world. These represent devices much(prenominal)(prenominal) as a keyboard, a mo design, switches, and the like.Definition (Contd. ) fleshs The microprocessor has a very narrow absorb on life. It bear understands binary topics. A binary digit is called a issue (which comes from binary digit). The microprocessor recognizes and processes a group of opuss to stick toher. This group of kidnappings is called a word. The way out of bits in a Microprocessors word, is a measure of its abilities. Definition (Contd. ) Words, Bytes, etc. The earliest microprocessor (the Intel 8088 and Motorolas 6800) recognized 8-bit words. They processed training 8-bits at a time. Thats why they argon called 8-bit pro cessors.They female genital organ holdle large figs, but in revisal to process these modus operandis, they broke them into 8-bit pieces and processed for apiece one group of 8-bits separately. Later microprocessors (8086 and 68000) were designed with 16-bit words. A group of 8-bits were referred to as a half-word or byte. A group of 4 bits is called a nibble. Also, 32 bit groups were given the name long word. Today, all processors manipulate at least 32 bits at a time and on that point exists microprocessors that stooge process 64, 80, 128 bits Definition (Contd. ) Arithmetic and logical system operations both microprocessor has arithmetic operations such as add and subtract as part of its instruction set. Most microprocessors impart have operations such as multiply and divide. Some of the newer ones exit have complex operations such as squargon root. In addition, microprocessors have logic operations as well. Such as AND, OR, XOR, shift unexpended, shift in force(p), etc. Again, the enactment and types of operations define the microprocessors instruction set and depends on the specific microprocessor. Definition (Contd. ) Stored in remembering First, what is wargonhousing? shop is the perspective where in formation is kept while not in current mathematical function. depot is a collection of storage devices. Usually, to each one storage device holds one bit. Also, in intimately kinds of retention, these storage devices ar group into groups of 8. These 8 storage sides roll in the hay scarce be approached together. So, one finish nevertheless read or write in terms of bytes to and form reposition. retrospection is ordinarily measurable by the number of bytes it fag hold. It is measured in Kilos, Megas and lately Gigas. A Kilo in computer wrangle is 210 =1024. So, a KB (KiloByte) is 1024 bytes. Mega is 1024 Kilos and Giga is 1024 Mega. Definition (Contd. ) Stored in remembering When a program is entered int o a computer, it is stored in reminiscence. thus as the microprocessor starts to execute the book of instruction manual, it brings the operating book of instructions from retrospection one at a time. retentiveness is also utilize to hold the information. The microprocessor reads (brings in) the data from remembering when it needs it and writes (stores) the results into computer retentiveness when it is done. Definition (Contd. ) Produces For the economic consumptionr to see the result of the execution of the program, the results must be presented in a human readable form. The results must be presented on an getup device. This derriere be the monitor, a paper from the printer, a dim-witted LED or m whatsoever other forms. A Microprocessor-based systemFrom the above description, we preserve draw the pursual block diagram to represent a microprocessor-based system comment Output remembering Inside The Microprocessor Internally, the microprocessor is made up of 3 main units. The Arithmetic/Logic Unit (ALU) The Control Unit. An array of historys for retentiveness data while it is being manipulated. Organization of a microprocessorbased system Lets expand the picture a bit. I/O introduce / Output ALU recital Array System Bus retentivity fixed storage dash Control reminiscence depot stores information such as instructions and data in binary format (0 and 1).It provides this information to the microprocessor whenever it is needed. Usually, there is a computer reminiscence sub-system in a microprocessor-based system. This sub-system includes The renders inside the microprocessor Read besides recollection (ROM) apply to store information that does not change. Random get at retrospection ( push) (also known as Read/ put out retention). determinationd to store information supplied by the user. Such as programs and data. retention lay out and mentiones The reposition board map is a picture representation of the a pproach ar part and shows where the different reposition chips be located within the orchestrate range. 000 0000 erasable programmable read-only store 3FFF 4400 appeal crop of EPROM assay appendress Range pile 1 RAM 2 RAM 3 wrap up Range of initiatory RAM Chip 5FFF 6000 visit Range of 2nd RAM Chip 8FFF 9000 A3FF A400 Address Range of third RAM Chip RAM 4 F7FF FFFF Address Range of 4th RAM Chip Memory To execute a program the user enters its instructions in binary format into the remembrance. The microprocessor then reads these instructions and whatever data is needed from holding, executes the instructions and places the results all in memory or produces it on an output device. The triple calendar method instruction execution model To execute a program, the microprocessor reads each instruction from memory, interprets it, then executes it. To use the right names for the cycles The microprocessor fetches each instruction, decodes it, consequently executes it. This sequence is continued until all instructions argon performed. Machine phraseology The number of bits that form the word of a microprocessor is fixed for that particular processor. These bits define a maximum number of combinations. For showcase an 8-bit microprocessor bed have at most 28 = 256 different combinations. However, in most microprocessors, not all of these combinations are apply. Certain patterns are chosen and charge specific meanings. Each of these patterns forms an instruction for the microprocessor. The complete set of patterns makes up the microprocessors mechanism language. The 8085 Machine Language The 8085 (from Intel) is an 8-bit microprocessor. The 8085 uses a amount of money of 246 bit patterns to form its instruction set. These 246 patterns represent only 74 instructions. The reason for the difference is that some (actually most) instructions have eightfold different formats. Because it is very difficult to enter the bit patterns corr ectly, they are commonly entered in hexadecimal instead of binary. For showcase, the combination 0011 1100 which translates into increase the number in the file called the accumulator, is usually entered as 3C. Assembly Language incoming the instructions using hexadecimal is quite easier than entering the binary combinations. However, it chill out is difficult to understand what a program written in hexadecimal does. So, each company defines a symbolic code for the instructions. These codes are called mnemonics. The mnemonic for each instruction is usually a group of letters that rede the operation performed. Assembly Language utilise the same example from before, 00111100 translates to 3C in hexadecimal (OPCODE) Its mnemonic is INR A. INR stands for increment immortalize and A is brusque for accumulator. Another example is 1000 0000, Which translates to 80 in hexadecimal. Its mnemonic is land B. Add history B to the accumulator and keep the result in the ac cumulator. Assembly Language It is important to remember that a machine language and its associated conference language are completely machine dependent. In other words, they are not transferable from one microprocessor to a different one. For example, Motorolla has an 8-bit microprocessor called the 6800. The 8085 machine language is very different from that of the 6800. So is the assembly language. A program written for the 8085 atomic number 50not be executed on the 6800 and vice versa. Assembling The Program How does assembly language get translated into machine language? there are twain ways 1st there is paw assembly. The programmer translates each assembly language instruction into its tantamount(predicate) hexadecimal code (machine language).Then the hexadecimal code is entered into memory. The other possibility is a program called an assembler, which does the translation automatically. 8085 Microprocessor Architecture 8-bit general decide p Capable of prognosticateing 64 k of memory Has 40 pins Requires +5 v power supply so-and-so operate with 3 MHz measure 8085 upward compatible Pins Power Supply +5 V relative frequency Generator is attached to those pins Input/Output/ Memory Read frame Multiplexed Address info Bus Address lock Enable Address Bus System Bus wires connecting memory & I/O to microprocessor Address Bus Unidirectional Identifying peripheral or memory localization data Bus Bidirectional shippingring data Control Bus Synchronization signals quantify signals Control signal Architecture of Intel 8085 Microprocessor Intel 8085 Microprocessor Microprocessor consists of Control unit control microprocessor operations. ALU performs data processing function. Registers provide storage intragroup to CPU. Interrupts Internal data mickle The ALU In addition to the arithmetic & logic circuits, the ALU includes the accumulator, which is part of every arithmetic & logic operation. Also, the ALU include s a temporary register used for holding data temporarily during the execution of the operation. This temporary register is not accessible by the programmer. Registers General Purpose Registers B, C, D, E, H & L (8 bit registers) Can be used singly Or groundwork be used as 16 bit register gibes BC, DE, HL H & L can be used as a data pointer (holds memory verbalize) Special Purpose Registers accumulator (8 bit register) Store 8 bit data Store the result of an operation Store 8 bit data during I/O transfer storage battery droops B C D E H L Program reciteer troop Pointer Address 6 8 selective information Flag Register 8 bit register shows the status of the microprocessor before/ later an operation S (sign signal flag), Z ( set flag), AC (auxillary gestate flag), P (parity flag) & CY (carry flag) D7 S D6 Z D5 X D4 AC D3 X D2 P D1 X D0 CY Sign Flag Used for indicating the sign of the data in the accumulator The sign flag is set if negative (1 negative) The sign flag is readjust if positive (0 positive) naught Flag Is set if result obtained after an operation is 0 Is set quest an increment or decrement operation of that register 10110011 + 01001101 1 00000000 take for Flag Is set if there is a carry or borrow from arithmetic operation 1011 0101 + 0110 1100 Carry 1 0010 0001 1011 0101 1100 1100 Borrow 1 1110 1001 Auxillary Carry Flag Is set if there is a carry out of bit 3 Parity Flag Is set if parity is veritable(a) Is cleared if parity is odd The Internal Architecture We have already discussed the general purpose registers, the aggregator, and the flags. The Program antipathetic (PC) This is a register that is used to control the sequencing of the execution of instructions. This register unendingly holds the speech communication of the next instruction. Since it holds an spread over, it must be 16 bits wide. The Internal Architecture The Stack pointer The dope pointer is also a 16-bit register that is used t o point into memory. The memory this register points to is a special area called the quid. The stack is an area of memory used to hold data that testament be retreived soon. The stack is usually accessed in a Last In First Out (LIFO) fashion. Non Programmable Registers counselling Register & Decoder pedagogy is stored in IR after fetched by processor Decoder decodes instruction in IR Internal quantify generator 3. 125 MHz internally 6. 5 MHz outwardly The Address and data Busses The overlay bus has 8 signal lines A8 A15 which are unidirectional. The other 8 traverse bits are multiplexed (time shared) with the 8 data bits. So, the bits AD0 AD7 are bi-directional and serve as A0 A7 and D0 D7 at the same time. During the execution of the instruction, these lines carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits. In put up to separate the address from the data, we can use a lock to save the p rise before the function of the bits changes. Demultiplexing AD7-AD0 From the above description, it becomes frank that the AD7 AD0 lines are serving a dual purpose and that they need to be demultiplexed to get all the information. The high order bits of the address remain on the bus for three clock periods. However, the low order bits remain for only one clock period and they would be lost if they are not saved externally. Also, notice that the low order bits of the address disappear when they are needed most. To make sure we have the entire address for the full-of-the-moon three clock cycles, we go out use an external hasp to save the value of AD7 AD0 when it is carrying the address bits.We use the ALE signal to change this latch. Demultiplexing AD7-AD0 8085 A15-A8 ALE AD7-AD0 Latch A7- A0 D7- D0 condition that ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes low, the address is saved and the AD7 AD0 lines can be used for their purp ose as the bi-directional data lines. Demultiplexing the Bus AD7 AD0 The high order address is displace on the address bus and hold for 3 clk periods, The low order address is lost after the initial clk period, this address needs to be hold however we need to use latch The address AD7 AD0 is connected as inputs to the latch 74LS373.The ALE signal is connected to the enable (G) pin of the latch and the OC Output control of the latch is grounded The Overall Picture Putting all of the concepts together, we get A15- A10 Chip involveion Circuit 8085 A15-A8 ALE AD7-AD0 Latch CS A9- A0 A7- A0 1K Byte Memory Chip WR RD IO/M D7- D0 RD WR Introduction to 8085 Instructions The 8085 Instructions Since the 8085 is an 8-bit device it can have up to 28 (256) instructions. However, the 8085 only uses 246 combinations that represent a total of 74 instructions. Most of the instructions have more(prenominal) than one format. These instructions can be class into five different groups Data Transfer operations Arithmetic trading operations Logic mathematical processs separate Operations Machine Control Operations Instruction and Data Formats Each instruction has twain parts. The first part is the task or operation to be performed. This part is called the opcode (operation code). The second part is the data to be operated on Called the operand. Data Transfer Operations These operations simply COPY the data from the microbe to the destination. MOV, MVI, LDA, and STA They transfer Data between registers.Data Byte to a register or memory position. Data between a memory fixing and a register. Data between an IO Device and the accumulator. The data in the source is not changed. The cardinal instruction The 8085 provides an instruction to place the 16-bit data into the register pair in one step. LXI Rp, (Load eXtended Immediate) The instruction LXI B 4000H will place the 16-bit number 4000 into the register pair B, C. The upper two digits are placed in the 1st register of the pair and the lower two digits in the 2nd . B 40 00 C LXI B 40 00H The Memory Register Most of the instructions of the 8085 can use a memory positioning in place of a register. The memory location will become the memory register M. MOV M B copy the data from register B into a memory location. Which memory location? The memory location is identify by the circumscribe of the HL register pair. The 16-bit circumscribe of the HL register pair are hardened as a 16-bit address and used to constitute the memory location. utilize the Other Register Pairs There is also an instruction for moving data from memory to the accumulator without raise uping the limit of the H and L register. LDAX Rp (LoaD gatherer eXtended) Copy the 8-bit content of the memory location identified by the Rp register pair into the aggregator. This instruction only uses the BC or DE pair. It does not suffer the HL pair. collateral Addressing Mode Using data in mem ory directly (without corrupting first into a Microprocessors register) is called Indirect Addressing. Indirect addressing uses the data in a register pair as a 16-bit address to identify the memory location being accessed. The HL register pair is always used in conjunction with the memory register M. The BC and DE register pairs can be used to load data into the Accumultor using indirect addressing.Arithmetic Operations Addition (ADD, ADI) Any 8-bit number. The confine of a register. The content of a memory location. Can be added to the contents of the accumulator and the result is stored in the accumulator. Subtraction (SUB, SUI) Any 8-bit number The contents of a register The contents of a memory location Can be subtracted from the contents of the accumulator. The result is stored in the accumulator. Arithmetic Operations relate to Memory These instructions perform an arithmetic operation using the contents of a memory location while they are still in memory. AD D SUB INR M M M / DCR M Add the contents of M to the Accumulator Sub the contents of M from the Accumulator gain/decrement the contents of the memory location in place. All of these use the contents of the HL register pair to identify the memory location being used. Arithmetic Operations Increment (INR) and Decrement (DCR) The 8-bit contents of any memory location or any register can be directly incremented or decremented by 1. No need to disturb the contents of the accumulator. Manipulating Addresses Now that we have a 16-bit address in a register pair, how do we manipulate it? It is assertable to manipulate a 16-bit address stored in a register pair as one entity using some special instructions. INX Rp DCX Rp (Increment the 16-bit number in the register pair) (Decrement the 16-bit number in the register pair) The register pair is incremented or decremented as one entity. No need to worry about a carry from the lower 8-bits to the upper. It is interpreted care of aut omatically. Logic Operations These instructions perform logic operations on the contents of the accumulator. ANA, ANI, ORA, ORI, XRA and XRI Source Accumulator and An 8-bit number The contents of a register The contents of a memory location Destination Accumulator ANA R/M ANI ORA ORI XRA XRI R/M R/M AND Accumulator With Reg/Mem AND Accumulator With an 8-bit number OR Accumulator With Reg/Mem OR Accumulator With an 8-bit number XOR Accumulator With Reg/Mem XOR Accumulator With an 8-bit number Logic Operations Complement 1s complement of the contents of the accumulator. CMA No operand Additional Logic Operations Rotate Rotate the contents of the accumulator one position to the left or right. RLC RAL RRC RAR Rotate the accumulator left. poker chip 7 goes to bit 0 AND the Carry flag. Rotate the accumulator left through the carry.Bit 7 goes to the carry and carry goes to bit 0. Rotate the accumulator right. Bit 0 goes to bit 7 AND the Carry flag. Rotate the accumulator right through the carry. Bit 0 goes to the carry and carry goes to bit 7. RLC vs. RLA Carry Flag RLC 7 6 5 4 3 2 1 0 Accumulator Carry Flag RAL 7 6 5 4 3 2 1 0 Accumulator Logical Operations Compare Compare the contents of a register or memory location with the contents of the accumulator. CMP R/M Compare the contents of the register or memory location to the contents of the accumulator. Compare the 8-bit number to the contents of the accumulator. CPI The compare instruction sets the flags (Z, Cy, and S). The compare is done using an internal subtraction that does not change the contents of the accumulator. A (R / M / ) Branch Operations Two types Unconditional outset. Go to a new location no matter what. Conditional branch. Go to a new location if the condition is true. Unconditional Branch JMP Address Jump to the address condition (Go to). chit-chat Address Jump to the address stipulate but apportion it as a social occasion. RET Return from a modus operan di. The addresses supplied to all branch operations must be 16-bits.Conditional Branch Go to new location if a qualify condition is met. JZ Address (Jump on Zero) Go to address specified if the Zero flag is set. JNZ Address (Jump on NOT Zero) Go to address specified if the Zero flag is not set. JC Address (Jump on Carry) Go to the address specified if the Carry flag is set. JNC Address (Jump on No Carry) Go to the address specified if the Carry flag is not set. JP JM Address (Jump on Plus) Address (Jump on Minus) Go to the address specified if the Sign flag is not set Go to the address specified if the Sign flag is set.Machine Control HLT Stop executing the program. NOP No operation Exactly as it says, do nothing. Usually used for balk or to replace instructions during debugging. Operand Types There are different ways for specifying the operand There may not be an operand (implied operand) CMA The operand may be an 8-bit number (immediate data) ADI 4FH The operand may be an internal register (register) SUB B The operand may be a 16-bit address (memory address) LDA 4000H Instruction Size Depending on the operand type, the instruction may have different sizes.It will occupy a different number of memory bytes. Typically, all instructions occupy one byte only. The ask oution is any instruction that contains immediate data or a memory address. Instructions that include immediate data use two bytes. One for the opcode and the other for the 8-bit data. Instructions that include a memory address occupy three bytes. One for the opcode, and the other two for the 16-bit address. Instruction with Immediate Date Operation Load an 8-bit number into the accumulator. MVI A, 32 Operation MVI A Operand The number 32 binary program Code 0011 1110 3E 1st byte. 011 0010 32 2nd byte. Instruction with a Memory Address Operation go to address 2085. Instruction JMP 2085 Opcode JMP Operand 2085 Binary code 1100 0011 C3 1000 0101 85 00 10 0000 20 1st byte. 2nd byte 3rd byte Addressing Modes The microprocessor has different ways of specifying the data for the instruction. These are called addressing modes. The 8085 has cardinal addressing modes Implied Immediate take aim Indirect CMA MVI B, 45 LDA 4000 LDAX B Load the accumulator with the contents of the memory location whose address is stored in the register pair BC). Data Formats In an 8-bit microprocessor, data can be represented in one of four formats ASCII BCD Signed Integer Unsigned Integer. It is important to recognize that the microprocessor deals with 0s and 1s. It deals with values as strings of bits. It is the job of the user to add a meaning to these strings. Data Formats Assume the accumulator contains the following value 0100 0001. There are four ways of reading this value It is an unsigned integer expressed in binary, the equivalent decimal number would be 65. It is a number expressed in BCD (Binary Coded Decimal) format. That wou ld make it, 41. It is an ASCII representation of a letter. That would make it the letter A. It is a string of 0s and 1s where the 0th and the 6th bits are set to 1 while all other bits are set to 0. ASCII stands for American Standard Code for discipline Interchange. sum upers & Time look intos Counters A curl forbid is set up by loading a register with a certain value Then using the DCR (to decrement) and INR (to increment) the contents of the register are updated. A hand-build is set up with a conditional jump instruction that interlaces buns or not depending on whether the count has reached the termination count.Counters The operation of a loop counter can be described using the following flowchart. format Body of loop Update the count No Is this lowest Count? Yes Sample ALP for implementing a loop Using DCR instruction MVI C, 15H handbuild DCR C JNZ LOOP Using a Register Pair as a iteration Counter Using a single register, one can repeat a loop for a maximum coun t of 255 times. It is possible to increase this count by using a register pair for the loop counter instead of the single register. A minor difficulty arises in how to study for the closing count since DCX and INX do not turn the flags. However, if the loop is smell for when the count becomes zero, we can use a small trick by ORing the two registers in the pair and then checking the zero flag. Using a Register Pair as a intertwine Counter The following is an example of a loop set up with a register pair as the loop counter. LXI B, 1000H LOOP DCX B MOV A, C ORA B JNZ LOOP grips It was shown in Chapter 2 that each instruction passes through different combinations of Fetch, Memory Read, and Memory Write cycles. knowledgeable the combinations of cycles, one can calculate how long such an instruction would require to complete. The table in Appendix F of the book contains a towboat with the title B/M/T. B for Number of Bytes M for Number of Machine wheel arounds T for Nu mber of T-State. time lags Knowing how many T-States an instruction requires, and retentiveness in mind that a T-State is one clock cycle long, we can calculate the time using the following formula Delay = No. of T-States / Frequency For example a MVI instruction uses 7 T-States. Therefore, if the Microprocessor is running at 2 MHz, the instruction would require 3. 5 Seconds to complete. Delay loops We can use a loop to produce a certain amount of time prevent in a program. The following is an example of a stand up loop MVI C, FFH LOOP DCR C JNZ LOOP 7 T-States 4 T-States 10 T-States The first instruction initializes the loop counter and is executed only once requiring only 7 T-States. The following two instructions form a loop that requires 14 T-States to execute and is repeated 255 times until C becomes 0. Delay Loops (Contd. ) We need to keep in mind though that in the hold water iteration of the loop, the JNZ instruction will fail and require only 7 T-States rather th an the 10. Therefore, we must deduct 3 T-States from the total delay to get an accurate delay calculation. To calculate the delay, we use the following formula Tdelay = TO + TL Tdelay = total delay TO = delay outside the loop TL = delay of the loop TO is the sum of all delays outside the loop. Delay Loops (Contd. ) Using these formulas, we can calculate the time delay for the earlier example TO = 7 T-States Delay of the MVI instruction TL = (14 X 255) 3 = 3567 T-States 14 T-States for the 2 instructions repeated 255 times (FF16 = 25510) cut by the 3 T-States for the final JNZ. Using a Register Pair as a Loop Counter Using a single register, one can repeat a loop for a maximum count of 255 times. It is possible to increase this count by using a register pair for the loop counter instead of the single register. A minor problem arises in how to test for the final count since DCX and INX do not falsify the flags. However, if the loop is looking for when the count become s zero, we can use a small trick by ORing the two registers in the pair and then checking the zero flag. Using a Register Pair as a Loop Counter The following is an example of a delay loop set up with a register pair as the loop counter. LXI B, 1000H LOOP DCX B MOV A, C ORA B JNZ LOOP 10 T-States 6 T-States 4 T-States 4 T-States 10 T-StatesUsing a Register Pair as a Loop Counter Using the same formula from before, we can calculate TO = 10 T-States The delay for the LXI instruction TL = (24 X 4096) 3 = 98301 T- States 24 T-States for the 4 instructions in the loop repeated 4096 times (100016 = 409610) reduced by the 3 TStates for the JNZ in the last iteration. Nested Loops Nested loops can be easy setup in Assembly language by using two registers for the two loop counters and updating the right register in the right loop. In the figure, the body of loop2 can be before or after loop1.Initialize loop 2 Body of loop 2 Initialize loop 1 Body of loop 1 Update the count1 No Is th is Final Count? Yes Update the count 2 No Is this Final Count? Yes Nested Loops for Delay Instead (or in conjunction with) Register Pairs, a nested loop structure can be used to increase the total delay produced. MVI B, 10H LOOP2 MVI C, FFH LOOP1 DCR C JNZ LOOP1 DCR B JNZ LOOP2 7 T-States 7 T-States 4 T-States 10 T-States 4 T-States 10 T-States Delay Calculation of Nested Loops The calculation remains the same except that it the formula must be applied recursively to each loop. Start with the inner loop, then plug that delay in the calculation of the outer(a) loop. Delay of inner loop TO1 = 7 T-States MVI C, FFH instruction TL1 = (255 X 14) 3 = 3567 T-States 14 T-States for the DCR C and JNZ instructions repeated 255 Delay Calculation of Nested Loops Delay of outer loop TO2 = 7 T-States MVI B, 10H instruction TL1 = (16 X (14 + 3574)) 3 = 57405 T-States 14 T-States for the DCR B and JNZ instructions and 3574 T-States for loop1 repeated 16 times (1016 = 1610) minus 3 for the final JNZ. TDelay = 7 + 57405 = 57412 T-States Total Delay TDelay = 57412 X 0. 5 Sec = 28. 06 millisecond Increasing the delay The delay can be further increase by using register pairs for each of the loop counters in the nested loops setup. It can also be increased by adding dummy instructions (like NOP) in the body of the loop. measure plat Representation of Various Control signals generated during writ of execution of an Instruction. Following Buses and Control Signals must be shown in a Timing plot juicyer nightspot Address Bus. Lower Address/Data bus ALE RD WR IO/M Timing Diagram Instruction A000h MOV A,B like cryptanalysis A000h 78 Timing Diagram Instruction A000h MOV A,B Corresponding cryptology A000h 78OFC 8085 Memory Timing Diagram Instruction A000h MOV A,B 00h T1 T2 T3 T4 A0h A15- A8 (Higher gild Address bus) Corresponding cryptogram A000h 78 78h ALE RD OFC WR 8085 Memory IO/M Op-code fetch cycle Timing Diagram Instruction A000h MVI A,45h Correspondin g tag A000h A001h 3E 45 Timing Diagram Instruction A000h MVI A,45h OFC MEMR Corresponding secret writing A000h A001h 3E 45 8085 Memory Timing Diagram T1 T2 T3 T4 T5 T6 T7 A0h A0h A15- A8 (Higher golf club Address bus) 00h 3Eh 01h 45h DA7-DA0 (Lower order address/data Bus) Instruction A000h MVI A,45h Corresponding Coding A000h A001h 3E 45 WR RD ALEIO/M Op-Code Fetch Cycle Memory Read Cycle Timing Diagram Instruction A000h LXI A,FO45h Corresponding Coding A000h A001h A002h 21 45 F0 Timing Diagram Instruction A000h LXI A,FO45h OFC MEMR MEMR Corresponding Coding A000h A001h A002h 21 45 F0 8085 Memory Timing Diagram Op-Code Fetch Cycle Memory Read Cycle Memory Read Cycle T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 A0h A0h A0h A15- A8 (Higher Order Address bus) 00h 21h 01h 45h 02h F0h DA7-DA0 (Lower order address/data Bus) ALE RD WR IO/M Timing Diagram Instruction A000h MOV A,M Corresponding Coding A000h 7E Timing Diagram Instruction A000h MOV A,MOFC MEMR Corresponding Coding A000h 7E 8085 Memory T iming Diagram T1 T2 T3 T4 T5 T6 T7 A0h Content Of Reg H A15- A8 (Higher Order Address bus) Instruction A000h MOV A,M Corresponding Coding A000h 7E 00h 7Eh L Reg Content Of M DA7-DA0 (Lower order address/data Bus) ALE RD WR IO/M Op-Code Fetch Cycle Memory Read Cycle Timing Diagram Instruction A000h MOV M,A Corresponding Coding A000h 77 Timing Diagram Instruction A000h MOV M,A OFC MEMW Corresponding Coding A000h 77 8085 Memory Timing Diagram T1 T2 T3 T4 T5 T6 T7 A0h Content Of Reg H A15- A8 (Higher Order Address bus)Instruction A000h MOV M,A Corresponding Coding A000h 77 00h 7Eh L Reg Content of Reg A DA7-DA0 (Lower order address/data Bus) ALE RD WR IO/M Op-Code Fetch Cycle Memory Write Cycle Chapter 9 Stack and Sub tours The Stack The stack is an area of memory identified by the programmer for temporary storage of information. The stack is a LIFO structure. Last In First Out. The stack normally grows backwards into memory. In other words, the programmer defines the bottom of the stack and the stack grows up into reducing address range. The Stack grows backwards into memory Memory bottom(a) of the Stack The Stack Given that the stack grows backwards into memory, it is customary to place the bottom of the stack at the end of memory to keep it as far away from user programs as possible. In the 8085, the stack is define by setting the SP (Stack Pointer) register. LXI SP, FFFFH This sets the Stack Pointer to location FFFFH (end of memory for the 8085). Saving Information on the Stack Information is saved on the stack by encourageing it on. It is retrieved from the stack by come forwarding it polish off. The 8085 provides two instructions carry on and embark on for storing information on the stack and retrieving it back. Both PUSH and POP work with register pairs ONLY.The PUSH Instruction PUSH B Decrement SP Copy the contents of register B to the memory location pointed to by SP Decrement BSP C F3 12 Copy the contents of register C to the memor y location pointed to by SP F3 FFFB FFFC FFFD FFFE FFFF 12 SP The POP Instruction POP D Copy the contents of the memory location pointed to by the SP to register E Increment SP Copy the contents of the memory location D E F3 12 pointed to by the SP to register D Increment SP F3 SP FFFB FFFC FFFD FFFE FFFF 12 Operation of the Stack During pushing, the stack operates in a decrement then store style. The stack pointer is decremented first, then the information is placed on the stack. During poping, the stack operates in a use then increment style. The information is retrieved from the top of the the stack and then the pointer is incremented. The SP pointer always points to the top of the stack. LIFO The order of PUSHs and POPs must be inverse of each other in order to retrieve information back into its original location. PUSH B PUSH D POP D POP B The PSW Register Pair The 8085 recognizes one additional register pair called the PSW (Program Status Word). This register pair i s made up of the Accumulator and the Flags registers. It is possible to push the PSW onto the stack, do whatever operations are needed, then POP it off of the stack. The result is that the contents of the Accumulator and the status of the Flags are go byed to what they were before the operations were executed. Subroutines A subroutine is a group of instructions that will be used repeatedly in different locations of the program. quite a than repeat the same instructions several times, they can be grouped into a subroutine that is called from the different locations. In Assembly language, a subroutine can exist anywhere in the code. However, it is customary to place subroutines separately from the main program. Subroutines The 8085 has two instructions for dealing with subroutines. The environ instruction is used to redirect program execution to the subroutine. The RTE insutruction is used to take place the execution to the handicraft routine. The refer Instruction CALL 4000H Push the address of the instruction instantly following the CALL onto the stack 2000 CALL 4000 2003 counter Load the program PC 2 0 0 3with the 16-bit address supplied with the CALL instruction. FFFB FFFC FFFD FFFE FFFF 3 20 SP The RTE Instruction RTE Retrieve the return address from the top of the stack Load the program counter with the return address. 2003 PC 4014 4015 RTE FFFB FFFC FFFD FFFE FFFF 03 20 SP Cautions The CALL instruction places the return address at the two memory locations straightway before where the Stack Pointer is pointing. You must set the SP correctly in the lead using the CALL instruction. The RTE instruction takes the contents of the two memory locations at the top of the stack and uses these as the return address. Do not modify the stack pointer in a subroutine. You will loose the return address.Passing Data to a Subroutine In Assembly Language data is passed to a subroutine through registers. The data is stored in one of the register s by the name program and the subroutine uses the value from the register. The other possibility is to use agreed upon memory locations. The calling program stores the data in the memory location and the subroutine retrieves the data from the location and uses it. Call by Reference and Call by Value If the subroutine performs operations on the contents of the registers, then these modifications will be transferred back to the calling program upon return from a subroutine. Call by reference If this is not desired, the subroutine should PUSH all the registers it needs on the stack on entry and POP them on return. The original values are restored before execution returns to the calling program. Cautions with PUSH and POP PUSH and POP should be used in opposite order. There has to be as many POPs as there are PUSHs. If not, the RET statement will pick up the wrong information from the top of the stack and the program will fail. It is not advisable to place PUSH or POP inside a loop. Conditional CALL and RTE Instructions The 8085 supports conditional CALL and conditional RTE instructions. The same conditions used with conditional JUMP instructions can be used. CC, call subroutine if Carry flag is set. CNC, call subroutine if Carry flag is not set RC, return from subroutine if Carry flag is set RNC, return from subroutine if Carry flag is not set Etc. A Proper Subroutine According to packet Engineering practices, a proper subroutine Is only entered with a CALL and exited with an RTE Has a single entry point Do not use a CALL statement to jump into different points of the same subroutine. Has a single exit point There should be one return statement from any subroutine. Following these rules, there should not be any confusion with PUSH and POP usage. The Design and Operation of Memory Memory in a microprocessor system is where information (data and instructions) is kept. It can be classified ad into two main types ? ? Main memory (RAM and ROM) Storage memory (Disks , CD ROMs, etc. ) The simple view of RAM is that it is made up of registers that are made up of flip-flops (or memory elements). ? ROM on the other hand uses diodes instead of the flip-flops to permanently hold the information. The number of flip-flops in a memory register determines the size of the memory word. Accessing Information in Memory For the microprocessor to access (Read or Write) information in memory (RAM or ROM), it needs to do the following Select the right memory chip (using part of the address bus). Identify the memory location (using the rest of the address bus). Access the data (using the data bus). 2 Tri-State Buffers An important circuit element that is used extensively in memory. This buffer is a logic circuit that has three states Logic 0, logic1, and high impedance. When this circuit is in high impedance mode it looks as if it is disconnected from the output completely.The Output is Low The Output is High High Impedance 3 The Tri-State B uffer This circuit has two inputs and one output. The first input behaves like the normal input for the circuit. The second input is an enable. ? ? If it is set high, the output follows the proper circuit behavior. If it is set low, the output looks like a wire connected to nothing. Output Input OR Input Output Enable Enable 4 The Basic Memory divisor The basic memory element is similar to a D latch. This latch has an input where the data comes in. It has an enable input and an output on which data comes out. Data Input D Data Output QEnable EN 5 The Basic Memory Element However, this is not safe. Data is always present on the input and the output is always set to the contents of the latch. To neutralise this, tri-state buffers are added at the input and output of the latch. Data Input D Data Output Q RD Enable EN WR 6 The Basic Memory Element The WR signal controls the input buffer. The bar over WR means that this is an lively low signal. So, if WR is 0 the input data reaches th e latch input. If WR is 1 the input of the latch looks like a wire connected to nothing. The RD signal controls the output in a similar manner. A Memory Register If we take four of these latches and connect them together, we would have a 4-bit memory register I0 WR I1 I2 I3 D Q EN EN RD D Q EN D Q EN D Q EN O0 O1 O2 O3 8 A group of memory registers D0 o D1 o o D2 o D3 WR D EN Q D EN Q D EN Q D EN Q D Q D EN Q D EN Q D EN Q Expanding on this scheme to add more memory registers we get the diagram to the right. EN D EN Q D EN Q D EN Q D EN Q D EN Q D EN Q D EN Q D EN Q o o o o RD D0 D1 D2 9 D3 remotely Initiated Operations External devices can initiate (start) one of the 4 following operations fix ?All operations are stopped and the program counter is reset to 0000. The microprocessors operations are interrupted and the microprocessor executes what is called a service routine. This routine handles the interrupt, (perform the necessary operations). Then the microprocessor returns to i ts previous operations and continues. Interrupt ? ? 10 A group of Memory Registers If we represent each memory location (Register) as a block we get the following I0 I1 I2 I3 WR EN0 EN1 EN2 EN3 RD O0 Input Buffers Memory Reg. 0 Memory Reg. 1 Memory Reg. 2 Memory Reg. 3 Output Buffers O1 O2 O3 11The Design of a Memory Chip Using the RD and WR controls we can determine the direction of flow either into or out of memory. Then using the appropriate Enable input we enable an individual memory register. What we have just designed is a memory with 4 locations and each location has 4 elements (bits). This memory would be called 4 X 4 Number of location X number of bits per location. 12 The Enable Inputs How do we produce these enable line? Since we can never have more than one of these enables active at the same time, we can have them encoded to reduce the number of lines coming into the chip.These encoded lines are the address lines for memory. 13 The Design of a Memory Chip So, the previo us diagram would now look like the following I I I I 0 1 2 3 WR A d d r e s s D e c o d e r Input Buffers Memory Reg. 0 Memory Reg. 1 Memory Reg. 2 Memory Reg. 3 Output Buffers A1 A0 RD O0 O1 O2 O3 14 The Design of a Memory Chip Since we have tri-state buffers on both the inputs and outputs of the flip flops, we can actually use one set of pins only. Input Buffers WR A1 A0 A D The chip Memory Reg. now look likeDthis would 0 d e 0 D0 A1 A0 D1 D2 D3 d r e s s c o d e r Memory Reg. 1 Memory Reg. 2 Memory Reg. Output Buffers D1 D2 D3 RD RD WR 15 The steps of writing into Memory What happens when the programmer issues the STA instruction? The microprocessor would turn on the WR control (WR = 0) and turn off the RD control (RD = 1). The address is applied to the address decoder which generates a single Enable signal to turn on only one of the memory registers. The data is then applied on the data lines and it is stored into the enabled register. 16 Dimensions of Memory Memory is usually m easured by two numbers its continuance and its width (Length X Width). ? ? The length is the total number of locations.The width is the number of bits in each location. The length (total number of locations) is a function of the number of address lines. of memory locations = 2( of address lines) 210 = 1024 locations (1K) ? So, a memory chip with 10 address lines would have Looking at it from the other side, a memory chip with 4K locations would need ? Log2 4096=12 address lines 17 The 8085 and Memory The 8085 has 16 address lines. That means it can address 216 = 64K memory locations. Then it will need 1 memory chip with 64 k locations, or 2 chips with 32 K in each, or 4 with 16 K each or 16 of the 4 K chips, etc. ow would we use these address lines to control the multiple chips? 18 Chip Select Usually, each memory chip has a CS (Chip Select) input. The chip will only work if an active signal is applied on that input. To allow the use of multiple chips in the make up of memory, we need to use a number of the address lines for the purpose of chip selection. These address lines are decoded to generate the 2n necessary CS inputs for the memory chips to be used. 19 Chip Selection caseful Assume that we need to build a memory system made up of 4 of the 4 X 4 memory chips we designed earlier.We will need to use 2 inputs and a decoder to identify which chip will be used at what time. The resulting design would now look like the one on the following slide. 20 Chip Selection Example RD WR D0 D1 RD WR A0 A1 CS RD WR A0 A1 CS RD WR A0 A1 CS RD WR A0 A1 CS A0 A1 A2 A3 2 X4 Decoder 21 Memory Map and Addresses The memory map is a picture representation of the address range and shows where the different memory chips are located within the address range. 0000 0000 EPROM 3FFF 4400 Address Range of EPROM Chip Address Range RAM 1 RAM 2 RAM 3 Address Range of 1st RAM Chip 5FFF 6000 Address Range of 2nd RAM Chip FFF 9000 A3FF A400 Address Range of 3rd RAM Chip RAM 4 F7FF FFFF A ddress Range of 4th RAM Chip 22 Address Range of a Memory Chip The address range of a particular chip is the list of all addresses that are mapped to the chip. An example for the address range and its relationship to the memory chips would be the Post positioning Boxes in the post office. Each quoin has its unique number that is assigned sequentially. (memory locations) The boxes are grouped into groups. (memory chips) The first box in a group has the number immediately after the last box in the previous group. 23 Address Range of a Memory ChipThe above example can be modified slightly to make it closer to our give-and-take on memory. Lets say that this post office has only 1000 boxes. Lets also say that these are grouped into 10 groups of 100 boxes each. Boxes 0000 to 0099 are in group 0, boxes 0100 to 0199 are in group 1 and so on. We can look at the box number as if it is made up of two pieces The group number and the boxs index within the group. So, box number 436 is t he thirty-sixth box in the 4th group. The upper digit of the box number identifies the group and the lower two digits identify the box within the group. 24The 8085 and Address Ranges The 8085 has 16 address lines. So, it can address a total of 64K memory locations. If we use memory chips with 1K locations each, then we will need 64 such chips. The 1K memory chip needs 10 address lines to uniquely identify the 1K locations. (log21024 = 10) That leaves 6 address lines which is the exact number needed for selecting between the 64 different chips (log264 = 6). 25 The 8085 and Address Ranges Now, we can break up the 16-bit address of the 8085 into two pieces A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Chip Selection Location Selection within the ChipDepending on the combination on the address lines A15 A10 , the address range of the specified chip is determined. 26 Chip Select Example A chip that uses the combination A15 A10 = 001000 would have addresses that range from 2000H to 23FFH. Keep in mind that the 10 address lines on the chip gives a range of 00 0000 0000 to 11 1111 1111 or 000H to 3FFH for each of the chips. The memory chip in this example would require the following circuit on its chip select input A 10 A 11 A 12 A 13 A 14 A 15 CS 27 Chip Select Example If we change the above combination to the following A 10 A 11 A 12 A 13 A 14 A 15 CSNow the chip would have addresses ranging from 2400 to 27FF. Changing the combination of the address bits connected to the chip select changes the address range for the memory chip. 28 Chip Select Example To illustrate this with a picture ? ? in the first case, the memory chip occupies the piece of the memory map identified as before. In the second case, it occupies the piece identified as after. before After 0000 2000 23FF 2400 27FF 0000 FFFF FFFF 29 High-Order vs. Low-Order Address Lines The address lines from a microprocessor can be classified into two types High-Order ? Low-Order ?